VLSI Design & Tech. Lab Practice

                                    VLSI Design and Technology

                                                                Fourth Year (SEM-7)

                                                                             Program Set

----------------------------------------------------------------------------------------------------------------------------------

1. Design and implement an 2/4 bit ALU for logical operations like AND, OR, XOR, XNOR, NAND using Spartan 3E FPGA.

• Download here

      2. Design and implement an Universal Shift Register with mode selection input for SISO, PISO, 

          SIPO, PIPO on FPGA.

• Download here

     

     3. Design a FIFO memory cell using FPGA.

• Download here

     4. Write a VHDL code for interfacing of 16*2 LCD with CPLD.

• Download here

     5. Using Microwind tool prepare CMOS layouts in selected technology, simulate output with and 

         without capacitive load for following designs-

• Inverter
• NAND
• NOR
• Half Adder
• 2:1 MUX
• 1 Bit SRAM

----------------------------------------------------------------------------------------------------------------------------------

• Note:- 

1. FPGA used here is of Spartan 3E family (XC3S100E), CP132 package with -4 speed
2. CPLD used here is of XC9500 family (XC9572), PC84 package with -15 speed
3. Software tool used for layouts Microwind v3.5  download full version here (foundry used-cmos018)